Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
IC layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design data, after which the mask can be used in a photolithographic process. The image created in the mask is often referred to as the intended or target image, while the image created on the substrate, by employing the mask in the photolithographic process is referred to as the printed image.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. Adding to the difficulty associated with increasingly smaller feature size is the diffractive effects of light. As light illuminates the mask, the transmitted light diffracts at different angles in different regions of the mask. These effects often result in defects where the intended image is not accurately “printed” onto the substrate during the photolithographic process, creating flaws in the manufactured device.
To address this problem, one or more resolution enhancement techniques are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. Examples of various resolution enhancement techniques are discussed in “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future,” Frank M. Schellenberg, Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377, which article is incorporated entirely herein by reference. One of these techniques, radiation amplitude control, is often facilitated by modifying the layout design data employed to create the lithographic mask. One way to implement this technique, for example, is to adjust the edges of the geometric elements in the layout design so that the mask created from the modified layout data will control the radiation amplitude in a desired way during a lithographic process. The process of modifying the layout design data in this manner is often referred to as “optical proximity correction” or “optical process correction” (OPC).
As previously noted, a layout design is made up of a variety of geometric elements, which typically are polygons. In some conventional “rule-based” optical proximity correction processes, geometric features that will increase the fidelity of the photolithographic process are automatically be added to geometric elements in the design. For example, some optical proximity correction processes may create serifs at one or more corners of a polygonal geometric element.
Still other types of optical proximity correction processes, sometimes referred to as “model-based” optical proximity correction processes, fragment the edges of the geometric elements in a design. More particularly, the individual edges of each geometric element are divided into smaller sections, often referred to as edge segments or edge fragments. The size of the fragments and which particular edges are to be fragmented are dependent upon parameters of the optical proximity correction process. The relative positions of the edge fragments relative are changed, and the new edge fragment locations are employed in a simulation of the actual lithographic process that will be used to manufacture the integrated circuit. The printed image produced by the lithographic process simulation is then compared with intended or “target” printed image, to see how closely the simulated printed image matches the target printed image. Based upon the degree of correspondence between the simulated printed image and the target printed image, the relative positions of the edge fragments are modified, and the lithographic process is simulated again using the new edge fragment locations. When the simulated printed image cannot be substantially improved by further displacement of the edge segments, it is often said that the optical proximity correction process has converged. This process of simulation, modification, and simulation is repeated until the simulated printed image sufficiently corresponds to the intended printed image, or until the optical proximity correction process has converged.
Layout designs can be very large. For example, one layout data file for a single layer of a field programmable gate array may be approximately 58 gigabytes. Accordingly, performing even a single iteration of an optical proximity correction process on a design is computationally intensive. Repeating a model-based optical proximity correction process until the simulated printed image matches the intended printed image, or until the optical proximity correction process has converged, only adds to the time required to finalize the layout design. Often, it can take as many as eight or more iterations for an optical proximity correction process to converge. Due to the number of required iterations of optical proximity correction and the complexity and size of modern layout designs, the time required to perform optical proximity correction is often measured in days. Even where advanced computer processing techniques are employed, performing model-based optical proximity correction may still take days.
One significant factor in model-based optical proximity correction is the model used to simulate the actual photolithographic manufacturing process. If the model is not accurate, then the corrected design data may still not print the desired image during the actual photolithographic manufacturing process. Accordingly, proper calibration of photolithographic manufacturing process simulation models is important.
At least two types of techniques for calibrating photolithographic manufacturing process simulation models conventionally have been used. Critical dimension (CD) based model calibration techniques rely on printing simple test structures, such as lines or rectangles of varying sizes, followed by measuring their widths and/or spaces at prescribed locations. CD measurements are typically collected in the form of a table consisting of gauges and their CD values, to which photolithographic manufacturing process simulation models then are calibrated by data fitting.
A second calibration technique, which uses contours of manufactured structures to augment CD-based model calibration, has been reported for many years now. Contour-based calibration uses contours extracted from top-down scanning electron microscope (SEM) images of printed features on a physical wafer. The contours of the actual manufactured structures then are compared with simulated printed images generated using the model. With contour-based calibration techniques, the calibration process is typically iterative, comparing SEM measured contours as input with simulated print images simulated using photolithographic manufacturing process simulation models that are improved with each iteration. In a hybrid calibration technique, the calibration uses a cost function that includes both CD and contour data.
Limitations as well as benefits of using either CD-based or contour-based model calibration have been enumerated. One of the primary metrology challenges in contour-based calibration is to properly import and overlay the measured physical contours (or measurement contours) onto the corresponding calibration features for the comparison. Because contour-based calibration typically includes root-mean-square (RMS) differences as a metric for comparing contour shapes, it is important that the measurement contours must be correctly aligned to be properly compared with the simulated printed image. Thus, contour-based calibration is sensitive to input misalignment of the measured contour data.
Some work has been made on accurately aligning measured contour data for model calibration. During post-metrology/pre-calibration steps, alignment is initially done by pattern matching, and then refined using edge placement error (EPE) criterion, which has improved model calibration quality. When a model for simulating a printed image is not yet available, alignment using the original layout design data (i.e., the target image) is perfectly acceptable, especially for structures with multiple features in the SEM image field of view (FOV). However, design features are not always printable on a wafer, and hence aligning SEM measured contours to the original layout design data is not always straightforward.